TCP Layer Synthesis

Well, after several coding setbacks i successfully synthesized/PARed/Generated a bit file for the project after adding the TCP header.There are two remaining bugs that need to be squashed: the TCP Checksum is not calculating correctly (strange since i simulated the core and it was calculating properly) and the GO signal is "sending" the packets more …

Construction and Simulation of TCP Header and Checksum

Over the last two weeks i began developing the TCP CRC algorithm for my project. This involved researching what data fields are used in calculating the CRC Checksum field of the TCP Header. Please see the post here for more information.After properly sequencing the Pseudo Header, TCP Header and TCP Data Payload into the CalcCRC …

Simulation of IP Header

Yes, this is the SECOND simulation of the IP Header core. The first simulation consisted of every field being completely static, thus after the first packet Wireshark would begin to label all following packets as "retransmit" packets.The reason for this digs slightly into the sequencing framework of IP. While IP doesn't have any handshaking, packets …

Header CRC Core

As many of you know, i decided to take my packet header creation "to the next level." i convinced myself that it would be cool to create a CRC calculation core rather than calculating the CRC of both the IP and TCP headers by hand and making them static.This would not only add a level …

Senior Project: AES Core

This last week was consisted of a LOT of work. i bit the bullet and finished the encryption core which required the complete development of a RoundKey module, which performs four 32-bit key lookups for every iteration during the encryption cycle.This module also had to keep track of the length of the key to determine …

Heartbeat LED Indicator

i know this is basically trivial, but it's also a good technique that i was taught by one of my teachers. If there is room in a design, use an LED as a "heartbeat" indicator which USES the same clock as the rest of the design. Also make it have enough logic in it that …

Senior Project: AES Core: Key Expansion Pt1

Wow, there was a lot of coding, recoding and recoding again for the heck of it this week. i wrote up a lot of documentation and block diagrams for the structure of my HDL to keep my mind from exploding (good thing).After completing the IP header last weekend, i decided to actually work on the …

Senior Design : Ethernet Communications Pt2

i picked up my almost-functioning Ethernet Initialization and test data transmission modules and started digging. i was looking for the reason why the Ethernet header was mis-configured.i found in my HDL the block of code that sends the configuration 9-bits to the SPI module, and realized that for the first byte, my HDL looked like:always@(posedge …

Senior Project: Ethernet Communications Pt1

After a week and a half, hashing out the proper initialization sequence for the ENC28J60 over SPI, i began to worry that my chip was dead. The reason: the link light on the Ethernet Jack on the Hub was not turning on.....not good.i looked at several resources trying to find a topic on WHY the …

Senior Project: SPI Debug Pt1

i started yesterday working with the SPI module that i wrote in Verilog. After i completed the signal integrity verifications and modifications, i had to start working with my designs inside the FPGA.i had written and simulated a three-part core that included the SPI module, an Ethernet Initialization module and a Test Packet module. All …