Senior Project: Ethernet Board Verification Pt2

Well, on the 22nd i started working with signal integrity verification between the Nexys2 and my Ethernet board. "Why would i do this", you may ask? Well, if the reader has ever done any extensive EE designs, it is known that there are "gremlins" or intermittent failures that occur in digital systems. For instance: when … Continue reading Senior Project: Ethernet Board Verification Pt2

Senior Project: Ethernet Board Verification Pt1

Before i start hammering heavily into the HDL and loading onto the FPGA, it is a good idea to confirm the correct operation of some of the core cornerstones of the board.So, i busted out the good old 16500 with the 16531A Oscilloscope Board and started probing.i began with verifying the clock signal was operating … Continue reading Senior Project: Ethernet Board Verification Pt1