Raspberry Pi 4 and Power Over Ethernet

I began watching Jeff Geerling on YouTube and one of his videos turned me on to the idea of using the one Raspberry Pi I use in my network topology in a format that DOESN’T require a power cord. I thoroughly enjoy cord organization which is one major reason I wanted to convert my Pi. … Continue reading Raspberry Pi 4 and Power Over Ethernet

TCP Layer Synthesis

Well, after several coding setbacks i successfully synthesized/PARed/Generated a bit file for the project after adding the TCP header.There are two remaining bugs that need to be squashed: the TCP Checksum is not calculating correctly (strange since i simulated the core and it was calculating properly) and the GO signal is "sending" the packets more … Continue reading TCP Layer Synthesis

Construction and Simulation of TCP Header and Checksum

Over the last two weeks i began developing the TCP CRC algorithm for my project. This involved researching what data fields are used in calculating the CRC Checksum field of the TCP Header. Please see the post here for more information.After properly sequencing the Pseudo Header, TCP Header and TCP Data Payload into the CalcCRC … Continue reading Construction and Simulation of TCP Header and Checksum

Simulation of IP Header

Yes, this is the SECOND simulation of the IP Header core. The first simulation consisted of every field being completely static, thus after the first packet Wireshark would begin to label all following packets as "retransmit" packets.The reason for this digs slightly into the sequencing framework of IP. While IP doesn't have any handshaking, packets … Continue reading Simulation of IP Header

Senior Project: Ethernet Communications Pt1

After a week and a half, hashing out the proper initialization sequence for the ENC28J60 over SPI, i began to worry that my chip was dead. The reason: the link light on the Ethernet Jack on the Hub was not turning on.....not good.i looked at several resources trying to find a topic on WHY the … Continue reading Senior Project: Ethernet Communications Pt1

Senior Project: SPI Debug Pt1

i started yesterday working with the SPI module that i wrote in Verilog. After i completed the signal integrity verifications and modifications, i had to start working with my designs inside the FPGA.i had written and simulated a three-part core that included the SPI module, an Ethernet Initialization module and a Test Packet module. All … Continue reading Senior Project: SPI Debug Pt1